NMOS transistors in advanced CMOS integrated circuits are frequently enhanced by a process sequence known as stress memorization technique (SMT), in which a layer of tensile material is deposited after the NMOS source and drain (NSD) ion implantation process is performed and before the source and drain anneal. During the anneal, the polycrystalline silicon (poly silicon) in the NMOS gate, which was partially amorphized by the NSD ion implant, recrystallizes with a grain configuration that exerts stress on the underlying NMOS channel when the tensile layer is removed. The resultant strain in the NMOS channel increases the mobility of the charge carriers, which desirably improves the on-state current.
The tensile stress film which is applied to NMOS transistors during SMT to improve NMOS performance is usually removed from PMOS transistors to prevent PMOS degradation. The degradation of the PMOS transistors by SMT is caused by two factors. First, hydrogen in the film enhances boron diffusion in the PMOS source and drain regions which increases short channel effects and also enhances the diffusion of boron through the PMOS gate dielectric into the channel region which also increases short channel effects. Second, PMOS hole carrier mobility is degraded by tensile stress. Short channel effects increase PMOS transistor standby power which is undesirable. Removing SMT from the PMOS transistors to avoid these detrimental effects increases manufacturing cost and cycletime.